The invention relates generally to digital electronic circuitry, and more particularly differential D flip-flop circuits.
Differential D flip-flops provide an important fundamental building block for digital systems. In some applications, differential D flip-flops provide a temporary storage function. In other applications, such as automatic test equipment, differential D flip-flops provide a way to synchronize differential tester data signals with timing signals.
As illustrated in FIG. 1, a conventional D-type differential flip-flop 10 typically includes respective master and slave cells 11 and 20. The master cell employs a data set circuit 12 that receives differential data on the application of a first clock edge to the input of a clock input circuit 14. On a subsequent edge of the clock signal, the data from the data set circuit is loaded and temporarily stored in a data store circuit 16. On the next clock edge, the data in the data store circuit is provided as the differential input data for the slave cell 20. The slave cell is constructed similar to the master cell 10, with its data set circuit receiving the output from the master cell and generating the differential output for the flip-flop. A more detailed description of this conventional construction is provided in U.S. Pat. No. 6,140,845 to Benachour.
For automatic test equipment applications, the clock input circuit 14 receives signals from a fractionally delayed clock known as a timing generator (not shown). For this application it is useful to include a reset circuit 18 in the differential D flip-flop described above. The reset feature provides the ability to force the differential output to a predetermined logic level. Conventionally, as shown in FIG. 2, reset circuitry typically includes several transistor switches QRS1-QRS4, to couple the differential output OUT, OUT* to a pullup/pulldown circuit 22.
While the conventional reset circuitry works well for relatively low-speed applications up to around 100 MHz, at higher frequencies the differential flip-flop tends to exhibit imbalances (i.e. output signal rise/fall times) in the output due to capacitive effects associated with the reset circuitry. Moreover, due to the large number of transistors employed to carry out the conventional reset function, the performance of the conventional differential D flip-flop is compromised.
What is needed and currently unavailable is a differential D flip-flop with reset capability that maintains a balanced differential output at high frequencies and maximizes performance. The differential flip-flop of the present invention satisfies these needs.
The high-speed differential D flip-flop of the present invention provides reset capability while maintaining a balanced differential output at high frequencies. Moreover, the reset capability is carried out with minimal circuitry to maximize circuit performance and reduce power dissipation and silicon area.
To realize the foregoing advantages, the invention in one form comprises a differential D flip-flop including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the input of the first data set circuit. The cell further includes a differential clock circuit and a differential reset circuit. The clock circuit having complementary clock inputs to alternately set and store data in the data set and data store circuits. The differential reset circuit is tied to the differential output and is operative in response to a reset signal to force the differential output to a predetermined logic level. The differential reset circuit includes matched complementary reset driver transistors to exhibit like parasitic capacitances. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell.
In another form, the invention comprises a timing circuit responsive to pattern timing data for use in automatic test equipment. The timing circuit includes a system clock for generating clock pulses of a predefined width and a differential D flip-flop. The differential D flip-flop has a timing data input to receive the pattern timing data, a clock input coupled to the system clock, an output, and a reset circuit. The reset circuit includes a reset input that is responsive to a reset signal to force the flip-flop output to a predetermined state. The timing circuit further includes a delay element coupled to the differential D flip-flop output and the differential D flip-flop reset input.